The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing an isolation layer composed of a lattice matched wide bandgap semiconductor material that is present between a substrate and a vertical stack of suspended semiconductor channel material nanosheets.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. One type of non-planar semiconductor device that has been touted as a viable option beyond the 7 nm technology node is a nanosheet containing device. By “nanosheet containing device” it is meant that the device contains one or more layers of semiconductor channel material portions having a vertical thickness that is substantially less than its width.
Nanosheet formation relies on the selective removal of one semiconductor material relative to another semiconductor material to form suspended nanosheets for gate-all-around devices. In the current state of the art, the gate wrapping the bottommost semiconductor channel material nanosheet of a vertical stack of suspended semiconductor channel material nanosheets contacts the semiconductor substrate which leads to potential parasitic leakage paths between the source region and the drain region through the semiconductor substrate. There is a need for providing nanosheet isolation for controlling the off-state leakage current, without interfering with the nanosheet CMOS device.